Synchronizing device for the receiver clock of a data transmission system using PSK modulation
US4137427A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1977 |
| Grant date | Jan 30, 1979 |
| Priority date | — |
| Expiry date | Jul 5, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention relates to a new clock synchronizing arrangement for use in the receiving device of a data transmission system employing PSK modulation. In PSK systems, the received signal x(t), for a given carrier angular frequency .omega..sub.c can be defined by its envelope and its phase r (t) and .phi.(t), respectively. r(t) and .phi.(t) can be expressed by: EQU r(t) =.sqroot.x.sup.2 (t) + x.sup.2 (t) and .phi.(t) = arctan x(t)/x(t) where x(t) is the Hilbert Transform of x(t). At the optimum signalling instant t.sub.opt, r(t.sub.opt) and .phi.(t.sub.opt) normalized (without the data) exhibit the minimum variance. The clock adjustment signal is derived from the variance of the envelope or the variance of the phase of the received signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.