Circuit means for collecting operational errors in IC chips and for identifying and storing the locations thereof
US4139818A · kind A · utility
25Cited by
3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1977 |
| Grant date | Feb 13, 1979 |
| Priority date | — |
| Expiry date | Sep 30, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes electronic circuits for use with test and diagnostic (T&D) means to collect errors orignating within integrated circuit (IC) chips during their operation in a system environment. Moreover, the circuits employ counters and a memory to identify and store the location of the defective chips so that prompt remedial action may be taken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.