Generalized performance power optimized PLA circuits
US4140921A · kind A · utility
8Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1977 |
| Grant date | Feb 20, 1979 |
| Priority date | — |
| Expiry date | Aug 31, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An array of parallel FET load circuits on an IC (integrated circuit) chip can have their respective signal delays equalized where their nodal capacitances are different or alternately can have their signal delays set for different durations to meet the needs of a subsequent circuit, by adjusting the current driving capacity of a driver driving each circuit to meet the desired delay requirements thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.