Semiconductor process using lapped substrate and lapped low resistivity semiconductor carrier
US4141135A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1976 |
| Grant date | Feb 27, 1979 |
| Priority date | — |
| Expiry date | Oct 12, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process intended for avoiding the "flip chip bonding" technique, well known for planar diodes, is provided. It is further applicable to mesa diodes and planar transistors. It comprises an essential step: the lapping of the substrate up to reduce its thickness to the same order of magnitude as the upper active layer of a semiconductor device, thus facilitating the cooling of the device through the substrate towards a heat sink. This essential step is made possible by virtue of a preliminary bonding on the upper layer of the semiconductor device of a block of silicon. According to a first alternative of the invention the block is finally eliminated and the device is a conventional one with a very thin substrate. According to a second alternative of the invention, the block is retained and lapped after addition of the heat sink, then metalized to provide a secondary way to the thermal flux.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.