Self-aligning double polycrystalline silicon etching process
US4142926A · kind A · utility
63Cited by
7References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1978 |
| Grant date | Mar 6, 1979 |
| Priority date | — |
| Expiry date | Jun 12, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer after being etched to form a predetermined pattern is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.