Semiconductor device and a logical circuit formed of the same
US4143390A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1977 |
| Grant date | Mar 6, 1979 |
| Priority date | — |
| Expiry date | Dec 12, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A plurality of N-type first regions are formed in matrix arrangement on a P-type semiconductor substrate, and a plurality of N-type second regions are respectively formed on first portions of the P-type semiconductor substrate which are positioned between the N-type first regions along each of the rows of the matrix arrangement. Depletion-type MOS transistors are formed of the second regions each acting as a channel and the N-type first regions disposed on each side of the second regions and acting as a source and a drain, gate electrodes are respectively formed on the second regions and second portions of the P-type semiconductor substrate which are positioned between the second regions, along each of columns of the matrix arrangement of the N-type first regions, and enhancement-type MOS transistors are formed of the second portions of the substrate under the gate electrodes, each of which forms a channel and the second regions disposed on each side of these second portions, which act as a source and drain. That is, the channel regions of the depletion-type MOS transistors function as the source or drain regions of the enhancement-type MOS transistors, the depletion-type MOS trans…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.