System and method for increasing microprocessor output data rate
US4144562A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1977 |
| Grant date | Mar 13, 1979 |
| Priority date | — |
| Expiry date | Jun 23, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed wherein a microprocessor having an eight-bit data bus and a sixteen-bit address bus is interconnected with a peripheral device to which a certain amount of data must be transferred at a data rate greater than is possible by utilizing the eight-bit data bus to accomplish the transfer. The system includes a microprocessor, a memory, and a peripheral device interconnected by the eight-bit data bus, the sixteen-bit address bus and a read-write conductor. The peripheral device includes an address code recognition circuit coupled to the data bus and one of the address lines, and also includes a fifteen-bit buffer connected to fifteen lines of the address bus. The address code recognition circuit generates an output which is gated with the read-write conductor to generate a clock signal which enables the data on the address bus to be loaded into the fifteen-bit buffer, from which it may be utilized by the peripheral device. During two microprocessor read cycles, two eight-bit bytes of data are loaded from the memory into the microprocessor via the data bus. Fifteen of these sixteen bits constitute data to be rapidly transferred to the peripheral device, an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.