Digital-to-analog converter employing two levels of decoding
US4146882A · kind A · utility
31Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1976 |
| Grant date | Mar 27, 1979 |
| Priority date | — |
| Expiry date | Aug 24, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/78
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.