Complementary latching disabling circuit
US4147964A · kind A · utility
11Cited by
3References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1978 |
| Grant date | Apr 3, 1979 |
| Priority date | — |
| Expiry date | Feb 9, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N3/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An oscillator responsive to a control signal generates a first signal at a first rate at an output terminal. A first transistor is coupled to the output terminal and to a load circuit. Normal operation of the load circuit depends upon the first transistor switching conductive states at the first rate. A second complementary type conductivity transistor forms a complementary disabling latch with the first transistor. A fault signal activates the latch and prevents the first transistor from switching conductive states, thereby disabling normal load circuit operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.