Inverter arrangements
US4149234A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1978 |
| Grant date | Apr 10, 1979 |
| Priority date | — |
| Expiry date | Feb 14, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/53835
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This invention provides an inverter circuit in which an output transformer has a tapped primary winding, one portion of which provides a collector load for a first transistor and the other portion of which provides a collector load for a second transistor, with a saturating transformer arranged to provide oscillatory positive feedback from the collectors to the bases of the transistors. The feedback paths from the saturating transformer to the bases of the transistors each includes the base/emitter path of a respective additional transistor and current is supplied to the collectors of the additional transistors in order to maintain operation during saturation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.