High speed store request processing control
US4149245A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1977 |
| Grant date | Apr 10, 1979 |
| Priority date | — |
| Expiry date | Jun 9, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiment provides storage control (PSCF) for overlapping the handling of processor store requests between their generation by an instruction execution means (IPPF) and their presentation to system main storage (MS). The embodiment uses a store counter, an inpointer counter, an outpointer counter, a translator pointer register, an output counter and a plurality of registers sets to process and control the sequencing of all store requests so that the PSCF can output them to MS in the order received from the IPPF. The embodiment uses the counters to coordinate the varying delays in PSCF processing of plural store request contained in different register sets and the translator. The store counter obtains independence between plural IPPF operand address (OA) registers which send the store requests and plural PSCF register sets which handle the store request. The number of OA registers is made independent of the number of register sets. The store counter is also used for serializing instruction control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.