Associative memory device with variable recognition criteria
US4149262A · kind A · utility
17Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1977 |
| Grant date | Apr 10, 1979 |
| Priority date | — |
| Expiry date | Apr 19, 1997 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAMs), which may be written into, or read from in conventional fashion. In a recognition mode, information is sequentially read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are then communicated back to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.