Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4151019A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1977 |
| Grant date | Apr 24, 1979 |
| Priority date | — |
| Expiry date | Aug 5, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/65
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.