Precharged FET ROS array
US4151603A · kind A · utility
2Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1977 |
| Grant date | Apr 24, 1979 |
| Priority date | — |
| Expiry date | Oct 31, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The problem of a race condition in the precharged drain type FET read only storage circuits is avoided in the invention disclosed herein, by applying the bit decode signal to the source of the array device, so that the drain cannot be discharged through the FET array device unless both the bit line connected to the source and word line connected to the gate have on-signals. Thus, the memory circuit can be operated in a faster cycle because the word and bit signals may be made coincident.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.