Low power write-once, read-only memory array
US4152627A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1977 |
| Grant date | May 1, 1979 |
| Priority date | — |
| Expiry date | Jun 10, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders or the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions. Also disclosed are PNP transistor devices (both vertical and lateral types) having P type emitter regions preferably made with a boron implant. A P-channel MOS device is also disclosed where the P+ source an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.