SPS CCD memory system with serial I/O registers
US4152780A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1977 |
| Grant date | May 1, 1979 |
| Priority date | — |
| Expiry date | Oct 20, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An organization of serial-parallel-serial (SPS) charged-coupled-device (CCD) memory arrays or blocks into a memory system is disclosed. Each memory block is comprised of an N-bit input register, an N-bit output register, N S-bit parallel registers and an N-bit I/O register. Data is bit-serially entered into the input register at a frequency F.sub.0 is bit-parallelly shifted through the parallel registers and simultaneously into the output register and the I/O register at a frequency F.sub.0 /N. Addressed read data are captured by the I/O register and are circulated continuously therein independently of the recirculation process performed by the output register, input register such that if I/O transfer rates are lower than the allowable refresh frequency of the charged-coupled-devices of the memory block, and if one or more refresh cycles are utilized, the addressed read data always remains available in the I/O register. Data is written into consecutively numerically increasing memory blocks such that a consecutive bit stream of data is loaded into the consecutive stages of the consecutive I/O registers during the read operation. This ensures an uninterrupted consecutive output bit …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.