High speed combinatorial digital multiplier
US4153938A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1977 |
| Grant date | May 8, 1979 |
| Priority date | — |
| Expiry date | Aug 18, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49963
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand. The multiplier includes circuitry for permitting encoding of the multiplier inputs in either binary unsigned or in two's compliment form. A multiplier mode control input controls whether the multip…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.