Speedup addressing device by detecting repetitive addressing
US4156290A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1976 |
| Grant date | May 22, 1979 |
| Priority date | — |
| Expiry date | Aug 26, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory addressing device for a memory divided in a plurality of elements each storing a plurality of information words. Each address for the memory comprises a first part which controls addressing means which address all the words of the memory elements stored in the address identified by said first part. All the addressed words are stored in corresponding output registers of the memory elements. The second part of the address enables the selection of the output register associated therewith. Consequently the reading operation for a block of information requires only one memory access time plus the read time of the output registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.