CMOS Analog multiplier for CCD signal processing
US4156924A · kind A · utility
6Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1977 |
| Grant date | May 29, 1979 |
| Priority date | — |
| Expiry date | Oct 17, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog multiplier for multiplying the signals derived from a charge coupled device (CCD) tap includes a balanced multiplier of a first conductivity-type and a buffer of a second conductivity-type coupled between the CCD tap and the balanced multiplier. The multiplier includes first and second transistors, the drains of which are coupled together to form an input. The buffer includes a load transistor coupled to the output of an amplifying transistor. Means are included for coupling the output of the amplifier transistor and the multiplier input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.