Fail-safe time delay circuit
US4157580A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1978 |
| Grant date | Jun 5, 1979 |
| Priority date | — |
| Expiry date | Jan 31, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01H47/043
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A fail-safe time delay circuit is provided to produce an output a predetermined time, and no less than a predetermined time after an input stimulus. The circuit includes a driving circuit for a pair of relays which are operated at slightly greater than 50% duty cycle and out of phase such that, except when the circuit is de-energized, at least one of the relays is always energized. The contacts of the two relays are employed in a balanced voltage amplifier to produce a bi-polar signal, with the magnitude of both polarities increasing, with the time required for the increase to a defined threshold establishing the time delay. A pair of threshold circuits are coupled to the output of the balanced voltage amplifier such that each threshold circuit (one responding to the positive portion, and the other the negative portion of the bi-polar output) is energized when the respective portion of the bi-polar signal is detected to reach the associated threshold. Each of the threshold circuits provides an input to a vital AND gate such that only when the excursion in the bi-polar signal exceeds the threshold of both threshold circuits will the vital AND gate produce an output to energize a loa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.