Technique for performing partial stores in store-thru memory configuration
US4157586A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1977 |
| Grant date | Jun 5, 1979 |
| Priority date | — |
| Expiry date | May 5, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.