Digital data resynchronization device
US4158108A · kind A · utility
2Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1978 |
| Grant date | Jun 12, 1979 |
| Priority date | — |
| Expiry date | Jan 24, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/073
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital data resynchronization device used as an interface circuit between the incoming junctions of a PCM switching center and the time division switch. It possesses a memory that contains one-bit words loaded at the rate of the incoming data and read at the rate of the local clock. As a means of avoiding conflict due to simultaneous read-and-write operations, two time slots in the local clock cycle are provided for write operations and one time slot for read operations. Application: RCM switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.