Memory array address buffer with level shifting
US4159540A · kind A · utility
4Cited by
2References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1978 |
| Grant date | Jun 26, 1979 |
| Priority date | — |
| Expiry date | Jul 31, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.