Galois field computer
US4162480A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 1977 |
| Grant date | Jul 24, 1979 |
| Priority date | — |
| Expiry date | Jan 28, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/726
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Errors are corrected in a cyclic encoded data stream, consisting of sequential groups of data bits and check bits, by means of a novel digital computer. The computer employs a stored program and is organized into three distinct substructures, each having an independent internal addressable memory and all capable of synchronous concurrent operation. An arithmetic unit substructure including a data memory implements finite field arithmetic operations upon received data. The arithmetic unit includes a Galois field manipulative subunit for producing finite field products and sums over the field GF(2.sup.5) from operands selected from three registers which derive data from the memory of the arithmetic unit, another register, or the result of a currently executed Galois field operation. The preferred embodiment is especially suitable for correcting data encoded in the Reed-Solomon (31,15) code. An address generator realizes address modification in the Galois field GF(2.sup.7), whereby consecutive addresses in data memory are characterized by a shift register sequence. The address generator includes a counter memory array and an equality test facility. Counter memory words of the address …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.