Semiconductor integrated circuit device with dual thickness poly-silicon wiring
US4162506A · kind A · utility
6Cited by
4References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 10, 1978 |
| Grant date | Jul 24, 1979 |
| Priority date | — |
| Expiry date | Jul 10, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device consisting of silicon gate MOS transistors. A polycrystalline silicon wiring layer is formed on a field insulating layer and connected with a polycrystalline gate electrode layer having a smaller thickness than that of the wiring layer, whereby the resistance of the wiring layer is reduced without making the gate electrode layer thick.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.