Three logic state input buffers
US4163907A · kind A · utility
6Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1977 |
| Grant date | Aug 7, 1979 |
| Priority date | — |
| Expiry date | Sep 16, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09425
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer having a single input and a pair of outputs providing three unambiguous logic output states including a first output connected directly to the input and a second output connected to the junction of a common gate configured FET and an impedance. The input is also connected to the source and body of the FET and a voltage source is connected to the impedance. The first output varies with the input for a first polarity input signal and the second output varies with the input for the opposite polarity input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.