Compensation circuit for an electrical signal mixer
US4163944A · kind A · utility
77Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1976 |
| Grant date | Aug 7, 1979 |
| Priority date | — |
| Expiry date | Dec 22, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/005
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The carrier suppression circuit of the present invention is utilized to minimize electrical imbalances within double-balanced mixers. The circuit operates upon a modulating signal, having at least two states so as to adjust the dwell time that the signal stays in a particular state to counteract the effects of electrical imbalance within the mixer. Minimization of the electrical imbalance provides a greater suppression of the carrier signal which, in turn, improves the quality of the signal both at the transmitter and at the receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.