Clock level shifting circuit
US4164716A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1978 |
| Grant date | Aug 14, 1979 |
| Priority date | — |
| Expiry date | May 22, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit for binary signals comprises a pair of equal value resistors connecting a common input signal to a pair of input terminals of a differential amplifier. A capacitor from one input terminal to ground stores the long term average input signal level for comparison with the instantaneous input signal level on the other input terminal. In another embodiment the range of input signal levels is modified by connecting equal value resistors from the input terminals to a voltage source. The invention provides amplification with minimum propagation delay, symmetrical propagation delay, a conventional logic level output signal and only requires a single power supply source for the amplifier circuit over a large range of input signal levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.