Serial-parallel-serial charge-coupled device memory having interlacing and ripple clocking of the parallel shift registers
US4165541A · kind A · utility
15Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1977 |
| Grant date | Aug 21, 1979 |
| Priority date | — |
| Expiry date | Dec 12, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial-parallel-serial organized charge-coupled device memory incorporates interlacing and ripple clocking of the parallel shift registers to achieve a high density of bits per unit area. The memory is organized as sixteen 4,096-bit blocks which are randomly accessible. The data in each of the sixteen blocks advance simultaneously at the rate of one bit per cycle. Each block has its own reference charge generator, sense amplifier, input-output decoder and CCD input circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.