Error control system for named data
US4166211A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1978 |
| Grant date | Aug 28, 1979 |
| Priority date | — |
| Expiry date | Apr 3, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/9017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error control system for named data functions in a hierarchical memory system environment requiring only a single error-control encoding for each data word used therein. Each level of memory in the hierarchy thereof includes a data word storage device preceded by an error checking circuit to validate and correct when possible data to be stored therein. A translator operates upon the data name of the data word to be stored to indicate the area or portion of the storage device in which the data word is to be stored. A directory table associates data names with data word locations in the storage device, and a search mechanism fed by the translator searches the directory table in the area or portion so indicated for a data word location in the storage device to store the data word. If a data word is not located in one level of memory, the next lower level of memory is searched for same. Data words may be stored and translated or shifted through the various levels of memory without further error control encoding thereof. Fetching occurs in essentially the reverse manner of storing with the caveat that the single encloder used for storing is replaced by a decoder or error checking cir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.