Dual field effect transistor structure for compensating effects of threshold voltage
US4166223A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1978 |
| Grant date | Aug 28, 1979 |
| Priority date | — |
| Expiry date | Feb 6, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual field effect transistor structure for reducing the effects of threshold voltage of one of the field effect transistors as reflected to a signal source device which is coupled thereto is disclosed. More specifically, a p-channel enhancement mode field effect transistor having a surface conduction channel and an n-channel depletion mode field effect transistor having a buried conduction channel are formed in a semiconductor structure such that both transistors have a common gate. A voltage potential is applied to the common gate to affect the first and second depletion regions in the semiconductor structure respectively associated with the enhancement mode and depletion mode transistors to render a quiescent threshold voltage of the enhancement mode transistor which is reflected to the measuring device. The semiconductor structure is initially electrically biased in conjunction with the voltage potential applied to the common gate to cause the first and second depletion regions to pinch off the buried conduction channel substantially eliminating current flow therethrough. The signal source device may be coupled to the source of the enhancement mode transistor to conduct a firs…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.