Digital frequency-lock circuit
US4166249A · kind A · utility
12Cited by
5References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 15, 1978 |
| Grant date | Aug 28, 1979 |
| Priority date | — |
| Expiry date | Feb 15, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0992
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital frequency-lock circuit has a binary rate multiplier connected between a fixed frequency oscillator and an output terminal to modify the oscillator output signal in accordance with a digital word. An up/down counter is arranged to supply the digital word to the rate multiplier in accordance with a count stored in the counter. The frequency of the rate multiplier output is compared with an input signal frequency during a cycle of the input signal to maintain a predetermined relationship between the compared frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.