Overshoot suppression circuitry for ternary pulses
US4167682A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1977 |
| Grant date | Sep 11, 1979 |
| Priority date | — |
| Expiry date | Nov 3, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
First and second indicating circuits connect a source of ternary pulses to a load. The ternary pulses are subject to baseline overshoot above a threshold level for a given period of time after the termination of each pulse. The first indicating circuit transmits an indication to the load responsive to ternary pulses of positive polarity above the threshold level. The second indicating circuit transmits an indication to the load responsive to ternary pulses of negative polarity above the threshold level. Transmission of an indication to the load by the second indicating circuit is inhibited for the given period of time after the termination of a ternary pulse of positive polarity above the threshold level to suppress negative baseline overshoot. Transmission of an indication to the load by the first indicating circuit is inhibited for the given period of time after the termination of a pulse of negative polarity above the threshold level to suppress positive baseline overshoot. The load is preferably an up-down counter that senses errors in the ternary pulse pattern. The indicating circuit each include a normally nonconducting switching transistor, inhibited by clamping circuits whi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.