Segmented error-correction system
US4168486A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1978 |
| Grant date | Sep 18, 1979 |
| Priority date | — |
| Expiry date | Jun 30, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing error control system for named data, a parity check matrix and apparatus for using same provides for single error correcting of the data word and for multiple error detecting in both the data word and data name. The parity check matrix and apparatus utilize two additional parity check bits (over that required by a system using a prior art SEC/DED Hamming code) to provide protection against single bit errors, eight contiguous bit errors (i.e., hardware stuck at logical one or logical zero for the whole eight contiguous bits), similar four contiguous bit errors, and faults covering the entire data name field (which could occur, for example, if a wrong data word was fetched from memory). The parity check matrix is segmented and mated to the error correctional requirements and prevalent error modes of each field being protected. In encoding, parity check bits are generated for the combined data word and associated data name field. In decoding, an overall parity check of the check bits, data word and data name is performed for distinguishing between odd and even errors. Further, the parity check matrix is invoked to generate a parity checking number for addressing a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.