Digital circuit generating a vital relay
US4168526A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1978 |
| Grant date | Sep 18, 1979 |
| Priority date | — |
| Expiry date | Mar 2, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04F1/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A microprocessor based vital delay circuit is provided which is arranged to emit an output no less than a predetermined time after an input stimulus. The predetermined time, which corresponds to the delay, is controlled by selecting the relationship between two quantities. A digital processor performs a series of computations on the two quantities, each computation is arranged to take unit time and by selecting the proper relationship between the two quantities, the total series of computations takes a predetermined amount of time. Before the output is allowed to occur, several checks are performed to insure that no hardware or software failures have erroneously generated the result. One novel checking technique insures that the clock frequency has not changed, and this technique is applicable to a wide variety of devices in which digital techniques are employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.