Shift register type memory device consisting of a plurality of memory chips
US4168534A · kind A · utility
1Cited by
2References
9Claims
0Family size
Assignees
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Key dates
| Filing date | Apr 11, 1977 |
| Grant date | Sep 18, 1979 |
| Priority date | — |
| Expiry date | Apr 11, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a shift register type memory device wherein a plurality of chips are connected to a single sense amplifier and wherein data to be stored is cyclically written into the chips, then when a predetermined loop within a chip for stored designated data is defective, the data is not stored in a loop within the chip adjacent to the defective loop, but is stored in a loop to be subsequently read out in a chip to be read out subsequently to the chip having the defective loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.