Paired least recently used block replacement system
US4168541A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1978 |
| Grant date | Sep 18, 1979 |
| Priority date | — |
| Expiry date | Sep 25, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set associative cache buffer organized with 2.sup.n blocks per set requires only 2n-1 age bits for determining the replacement block within a set. When the cache buffer is addressed and the data sought is not found therein, the age bits determine which block of data in the set should be replaced with new data from the main memory. The block replaced may be either the least recently used block or one of the two least recently used blocks. The replacement logic is such that the buffer may be expanded from two to four blocks per set with minimal impact on the replacement logic. In addition, provision is made for disabling faulty blocks thus allowing the cache buffer and main memory behind it to be utilized in a degraded mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.