Digital carrier correction circuit
US4169246A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1976 |
| Grant date | Sep 25, 1979 |
| Priority date | — |
| Expiry date | Dec 6, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0073
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A carrier correction circuit accepts a serial digital data input stream having an underlying carrier frequency associated with it and generates a corrected carrier signal synchronized with the underlying carrier frequency. The input stream may, for example, be a serial output of an analog-to-digital converter having a differential phase shift keyed analog signal applied to its analog input, the underlying carrier frequency being the carrier frequency of the DPSK signal. The carrier correction circuit includes a phase detector which receives the serial digital data input stream and two representations of the recovered carrier which are shifted in phase from each other by 90.degree.. Each of these representations of the recovered carrier is mixed with the serial digital data input stream by means of first and second mixer circuits, and the results are loaded into first and second serial accumulators, which accumulate, respectively, the average products of the two mixer circuits over a certain time period. A magnitude comparator periodically generates an error signal by comparing the magnitudes of the first and second serial accumulators. The carrier correction circuit includes a carr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.