Cache control for concurrent access
US4169284A · kind A · utility
30Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1978 |
| Grant date | Sep 25, 1979 |
| Priority date | — |
| Expiry date | Mar 7, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure enables concurrent access to a cache by main storage and a processor by means of a cache control which provides two cache access timing cycles during each processor storage request cycle. The cache is accessible to the processor during one of the cache timing cycles and is accessible to main storage during the other cache timing cycle. No alternately accessible modules, buffering, delay, or interruption is provided for main storage line transfers to the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.