Photo detector input circuit
US4173723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1978 |
| Grant date | Nov 6, 1979 |
| Priority date | — |
| Expiry date | Jan 12, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/953
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An improved input circuit is provided for an array of photo detectors. For each photo detector in the array, the circuit utilizes a first FET with a source for coupling to an output of a photo detector, a gate coupled to a first gate voltage, and a drain for coupling to an output circuit. The first gate voltage is provided by a feedback circuit which utilizes matched properties of adjacent FETs. In one embodiment, FETs are used in an open loop feedback circuit to reduce the input impedance seen by the photodiode at the source of the first FET. A similar objective is accomplished in another embodiment utilizing FETs in a closed loop feedback circuit. Further embodiments utilize FETs arranged as a differential amplifier with active loads to provide a low input impedance and a virtual ground at the source of the first FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.