Time-shared, multi-phase memory accessing system having automatically updatable error logging means
US4174537A · kind A · utility
13Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 1977 |
| Grant date | Nov 13, 1979 |
| Priority date | — |
| Expiry date | May 31, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Automatically updatable error logging means incorporated in a multi-phase, bit addressable, variable field memory system. The memory system is partitioned into a plurality of individually addressable memory stacks and employs time-shared accessing of the memory stacks along with time-shared error detection and correction which is used with the error logging means to provide for automatic logging of the detected errors during memory accesses on a priority basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.