Method and circuit for checking integrated circuit chips
US4176258A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 1978 |
| Grant date | Nov 27, 1979 |
| Priority date | — |
| Expiry date | May 1, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1637
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and circuit for checking integrated circuit chips without the use of external checking circuits. Chips are fabricated with an error-checking circuit on each chip. Data from data processing logic on each chip is outputted via a first path to one input of its respective checking circuit and via a second path to an output pin or pins. The output pin on each chip is also connected via a third path to the other input of its checking circuit. The input and output pins of each chip are wired in parallel. A separate check input pin is provided to each integrated circuit chip. On one chip this pin is activated, making this first chip the checker. On the other chip, the check input pin is deactivated. On the chip which is the checker, the output from the data processing logic is prevented from being passed externally via the first path, but is allowed to enter the checking circuit via the second path. The output from the other chip, which is wired in parallel with the first chip, enters the error-checking circuit on the first chip via the third path. The outputs from the first chip and the second chip are thus checked with respect to each other in the error-checking circuit, and if th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.