Method of connecting semiconductor structure to external circuits
US4176443A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1978 |
| Grant date | Dec 4, 1979 |
| Priority date | — |
| Expiry date | Nov 3, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon wafer, having a front surface with disjointed contact areas and a uniform rear surface, is provided at the contact areas of its front surface with respective pads each comprising a base layer of aluminum, a first intermediate layer of chromium or titanium, a second intermediate layer of nickel and an outer layer of gold or palladium. The rear surface is covered with a base layer of gold (or of a gold/arsenic alloy in the case of N-type silicon), a first intermediate layer of chromium, a second intermediate layer of nickel and an outer layer of gold or palladium to which a film of low-melting bonding agent (lead/tin solder) is applied. After testing and elimination of unsatisfactory wafer sections, the remaining sections are separated into dies placed on a conductive substrate; an extremity of a respective terminal lead, encased in a similar bonding agent, is then placed on the outer layer of each contact pad. All soldering operations are simultaneously performed in a furnace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.