Patent · US Expired

Integrated circuit arrangement with means for avoiding undesirable capacitive coupling between leads

US4177480A · kind A · utility

16Cited by

5References

22Claims

0Family size

Assignee

Licentia Patent-Verwaltungs-GmbH · DE

Inventors

Kurt Hintzmann · Leingarten, DE
Reinhold Kaiser · Heilbronn, DE
Wolfgang Link · Schwaigern, DE
Willy Minner · Schwaigern, DE
Dieter Mutz · Leingarten, DE
Manfred Salomon · Leingarten, DE
Arnim Wingert · Heilbronn, DE

Key dates

Filing date	Apr 26, 1978
Grant date	Dec 4, 1979
Priority date	—
Expiry date	Apr 26, 1998

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10T29/49121
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit arrangement comprises a semiconductor body carrying an integrated circuit which is embedded in an insulating material casing together with a plurality of flat strip lines for making electrical connection with the semiconductor body, and a layer of electrically conductive material in or on the casing in a plane substantially parallel to the flat strip lines only on the side of the semiconductor body in which the construction elements forming the integrated circuit are located.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.