Floating point data processor having fast access memory means
US4179734A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1977 |
| Grant date | Dec 18, 1979 |
| Priority date | — |
| Expiry date | Oct 31, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3896
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle. Memory registers comprise a data pad having a plurality of selectable stack registers and means for writing information into said data pad during one clock cycle for retrieval during the next clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.