Single transistor memory cell employing an amorphous semiconductor threshold device
US4180866A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1977 |
| Grant date | Dec 25, 1979 |
| Priority date | — |
| Expiry date | Aug 1, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single transistor memory cell wherein the memory cell is provided by the base collector capacitance of the transistor in the integrated circuit chip. Mounted on top the chip in electrical contact with the base of the transistor is an amorphous semiconductor threshold device employing a tellurium based chalcogenide such that when a charge is applied to the terminal of the device opposite the transistor base, the device will be switched to a high conducting state until such time as the base collector capacitance has been charged and then the threshold device will be switched to a low-conducting state. Specifically, the amorphous threshold device employs Ge.sub.15 Te.sub.81 Sb.sub.2 S.sub.2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.