Automatic control of integrated circuit trimming
US4182024A · kind A · utility
27Cited by
2References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1977 |
| Grant date | Jan 8, 1980 |
| Priority date | — |
| Expiry date | Dec 15, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/26
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
In a monolithic integrated circuit having a combination of bipolar and junction field effect transistors, a pulsed laser is employed to trim the transistors to achieve balanced circuit performance. The laser is applied to individual circuits in wafer form using a step and repeat operation. Each circuit is measured, the transistor to be trimmed determined and a first trim performed. The circuit is remeasured and, if still out of specification, retrimmed. The process is repeated until a desired degree of balance is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.