High yield processing for silicon-on-sapphire CMOS integrated circuits
US4183134A · kind A · utility
31Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1978 |
| Grant date | Jan 15, 1980 |
| Priority date | — |
| Expiry date | Dec 11, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein a technique for constructing a complementary MOS device on a sapphire substrate so that the surface of the device is planarized, the P-channel and N-channel devices are in substantially correct registration, the threshold voltage for the back-channel leakage effect inherent in sapphire substrate device to occur is increased, and the areas of gate oxidation are pseudo self-aligned so as to minimize overlap of the gate oxide with the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.