In-situ test and diagnostic circuitry and method for CML chips
US4183460A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1977 |
| Grant date | Jan 15, 1980 |
| Priority date | — |
| Expiry date | Dec 23, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "Open" Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.