Fault-tolerant clock signal distribution arrangement
US4185245A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1978 |
| Grant date | Jan 22, 1980 |
| Priority date | — |
| Expiry date | May 15, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant clock signal distribution system for a plurality of equipment units is disclosed. Fault tolerance is achieved by independent bussing of clock signals from each of a pair of duplicated clock sources to a plurality of clock receiver units, each receiver unit associated with one of the plurality of equipment units and including sequential logic apparatus operative to examine the two clock signal trains bussed to the clock receiver unit and to ignore that signal train that phase lags the other. In case the phase leading clock source or its transmission bus fails, the remaining clock signal takes over. Because the outputs of the duplicated clock sources are distributed over separate busses, either source may comprise the phase-leading clock at any particular clock receiver unit. The phase difference between the two clock source outputs is kept small enough such that any resultant irregularity in the clock receiver unit output upon failure of one of the two clock sources or transmission busses will not affect the normal operation of the equipment units served by the clock distribution arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.